STC62WV2568 revisio n 1.1 jan. 2004 1 a17 very low power/voltage cmos sram 256k x 8 bit ? wide vcc operation voltage : 2.4v~5.5v ? very low power consumption : vcc = 3.0v c-grade : 22ma (@55ns) operating current i- grade : 23ma (@55ns) operating current c-grade : 17ma (@70ns) operating current i- grade : 18ma (@70ns) operating current 0.3ua (typ.) cmos standby current vcc = 5.0v c-grade : 53ma (@55ns) operating current i- grade : 55ma (@55ns) operating current c-grade : 43ma (@70ns) operating current i- grade : 45ma (@70ns) operating current 1.0ua (typ.) cmos standby current ? high speed access time : -55 55ns -70 70ns ? automatic power down when chip is deselected ? three state outputs and ttl compatible t he STC62WV2568 is a high performance, ve ry low pow er cmos static random access memory organized as 262,144 words by 8 bits and operates from a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 0.3ua at 3.0v /25 o c and maximum access time of 55ns at 3.0v/85 o c. easy memory expansion is provided by an active low chip enable (ce1), an active high chip enable (ce2), and active low output enable (oe) and three-state output drivers. t he STC62WV2568 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the STC62WV2568 is available in dice form, jedec standard 32 pin 450mil plastic sop, 8mmx13.4mm stsop and 8mmx20mm tsop. ? description ? features ? block diagram ? product family ? pin configurations stc international limited . reserves the right to modi fy document contents without notice. address input buffer row decoder memory array 1024 x 2048 column i/o write driver sense amp column decoder data buffer output address input buffer a8 a3 a2 a1 a10 data buffer input control gnd vdd oe dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 a16 a5 a4 a6 a7 a15 a13 8 8 8 8 16 256 2048 1024 20 a14 a12 a9 STC62WV2568 a11 a0 oe a10 ce1 dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3 a11 a9 a8 a13 we ce2 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 ? STC62WV2568tc STC62WV2568stc STC62WV2568ti STC62WV2568sti 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe we ce1 ce2 stc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a17 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd vcc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 dq7 dq6 dq5 dq4 dq3 ? STC62WV2568s STC62WV2568si 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 power dissipation speed ( ns ) standby ( i ccsb1 , max ) operating ( i cc , max ) product family operating temperature vcc range 55ns :3.0~5.5v vcc=3.0v vcc=3.0v pkg type STC62WV2568 dc dice STC62WV2568 tc tsop-32 STC62WV2568 stc stsop-32 STC62WV2568 sc +0 o c to +70 o c 2.4v ~5.5v 55/70 3.0ua 17ma sop-32 STC62WV2568 di dice STC62WV2568 ti tsop-32 STC62WV2568 sti stsop-32 STC62WV2568 si -40 o c to +85 o c 2.4v ~ 5.5v 55/70 5.0ua 18ma sop-32 vcc=5.0v vcc=5.0v 10ua 30ua 43ma 45ma 70ns :2.7~5.5v ? fully static operation ? data retention supply voltage as low as 1.5v ? easy expansion with ce2, ce1, and oe options 70ns 70ns .com .com .com
STC62WV2568 revisio n 1.1 jan. 2004 2 name function a0-a17 address input these 18 address inputs select one of the 262,144 x 8-bit words in the ram ce1 chip enable 1 input ce2 chip enable 2 input ce1 is active low and ce2 is active high. both chip enables must be active when data read from or write to the device. if either chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. dq0-dq7 data input/output ports these 8 bi-directional ports are used to read data from or write data into the ram. vcc power supply gnd ground ? truth table ? pin descriptions stc c in input capacitance v in =0v 6 pf c dq input/output capacitance v i/o =0v 8 pf range ambient temperature vcc commercial 0 o c to +70 o c 2.4v ~ 5.5v industrial -40 o c to +85 o c 2.4v ~ 5.5v ? absolute maximum ratings (1) ? operating range ? capacitance (1) (ta = 25 o c, f = 1.0 mhz) 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not 100% tested. symbol parameter rating units v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t bias temperature under bias -40 to +85 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma mode we ce1 ce2 oe i/o operation vcc current xhxx not selected (power down) xxlx high z i ccsb , i ccsb1 output disabled h l h h high z i cc read h l h l d out i cc write l l h x d in i cc STC62WV2568 symbol parameter conditions unit max. .com .com .com .com
STC62WV2568 revisio n 1.1 jan. 2004 3 stc symbol parameter test conditions min. typ. (1) max. units v dr vcc for data retention ce1 R Q R Q R Q R Q R Q R Q R Q .com .com .com .com
STC62WV2568 revision 1.1 jan. 2004 4 ? ac electrical characteristics ( ta = -40 o c to + 85 o c) read cycle ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , stc STC62WV2568 ? ac test conditions (test load and input/output reference) input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc output load c l = 100pf+1ttl c l = 30pf+1ttl jedec parameter name parameter name description (vcc = 3.0~5.5v) (vcc = 2.7~5.5v) unit t avax t rc read cycle time 55 -- -- 70 -- -- ns t avqv t aa address access time -- -- 55 -- -- 70 ns t e1lqv t acs1 chip select access time -- -- 55 -- -- 70 ns t e2hov t acs2 -- -- 55 -- -- 70 ns t glqv t oe output enable to output valid -- -- 30 -- -- 35 ns t e1lqx t clz1 chip select to output low z 10 -- -- 10 -- -- ns t e2hox t clz2 10 -- -- 10 -- -- ns t glqx t olz output enable to output in low z 5----5---- ns t e1hqz t chz1 chip deselect to output in high z -- -- 30 -- -- 35 ns t e2hqz t chz2 -- -- 30 -- -- 35 ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t axox t oh data hold from address change 10 -- -- 10 -- -- ns min. typ. max. min. typ. max. chip select access time (ce2) (ce1) chip select to output low z (ce1) (ce2) chip deselect to output in high z (ce1) (ce2) cycle time : 55ns cycle time : 70ns .com .com .com .com
STC62WV2568 revision 1.1 jan. 2004 5 stc read cycle3 (1,4) read cycle2 (1,3,4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce1 = v il and ce2= v ih. 3. address valid prior to or coincident with ce1 transition low and/or ce2 transition high. 4. oe = v il . 5. the parameter is guaranteed but not 100% tested. t clz (5) d out ce2 ce1 (5) t acs2 t acs1 t oh t rc t oe t clz2 t chz2 (2,5) d out ce2 ce1 oe address (5) t clz1 (5) t acs1 t acs2 t chz1 (1,5) t ohz (5) t olz t aa t chz1, t chz2 STC62WV2568 ? switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh .com .com .com .com
STC62WV2568 revision 1.1 jan. 2004 6 stc STC62WV2568 ? switching waveforms (write cycle) write cycle1 (1) t wr1 t wc (3) t cw (11) (11) t cw (2) t wp t aw t ohz (4,10) t as t wr2 (3) t dh t dw d in d out we ce2 ce1 oe address (5) (5) ? ac electrical characteristics ( ta = -40 o c to + 85 o c ) write cycle jedec parameter name parameter name description (vcc = 3.0~5.5v) (vcc = 2.7~5.5v) unit t avax t wc write cycle time 55 -- -- 70 -- -- ns t e1lwh t cw chip select to end of write 55 -- -- 70 -- -- ns t avwl t as address setup time 0 -- -- 0 -- -- ns t avwh t aw address valid to end of write 55 -- -- 70 -- -- ns t wlwh t wp write pulse width 30 -- -- 35 -- -- ns t whax t wr1 write recovery time (ce1,we) 0 -- -- 0 -- -- ns t e2lax t wr2 (ce2) 0 -- -- 0 -- -- ns t wlqz t whz write to output in high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 25 -- -- 30 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t whox t ow end of write to output active 5 -- -- 5 -- -- ns min. typ. max. min. typ. max. write recovery time cycle time : 55ns cycle time : 70ns .com .com .com .com
STC62WV2568 revision 1.1 jan. 2004 7 stc notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce1 and ce2 active and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce1 or we going high or ce2 going low at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce1 low transition or the ce2 high transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce1 is low and ce2 is high during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce1 going low or ce2 going high to the end of write. write cycle2 (1,6) t wc t cw (11) (11) t cw (2) t wp t aw t whz (4,10) t as t wr2 (3) t dh t dw d in d out we ce2 ce1 address (5) (5) t ow (7 ) (8 ) (8 ,9 ) STC62WV2568 .com .com .com .com
STC62WV2568 revision 1.1 jan. 2004 8 ? ordering information stc ? package dimensions stsop - 32 STC62WV2568 note: stc (stc international limited.) assumes no responsibility for the application or use of any product or circuit described herein. stc does not authorize i ts products for use as critical components in any application in which the failure of the stc product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. package s: sop t: tsop (8mm x 20mm) st: small tsop (8mm x 13.4mm) d: dice STC62WV2568x x y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material -: normal g: green p: pb free .com .com .com .com
STC62WV2568 revision 1.1 jan. 2004 9 stc ? package dimensions (continued) tsop - 32 STC62WV2568 base metal with plating c c1 section a-a b1 b sop -32 .com .com .com
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